Just over a decade ago, ferroelectricity – the presence of a permanent reorientable dipole – was reported in doped hafnium oxide thin films. This report generated a great deal of excitement as the inherent silicon compatibility of HfO₂, coupled with the extreme thinness of the films that exhibited the ferroelectric response promised to overcome a number of technological hurdles limiting utilization of ferroelectrics in microelectronics. In spite of the great promise and significant worldwide research efforts, this material has not yet been mass deployed owing to a number of challenges. These include: 1) performance variability for nominally identical materials and devices produced by different research groups, 2) performance variability as films are used in devices – i.e. polarization changes with use. Virtually all of these issues can be traced to phase impurities in the films – i.e. the ferroelectric phase co-exists with non-ferroelectric phases. In this presentation, I will highlight our group’s efforts to better understand this potentially game changing material and to overcome some of these challenges. Two major phase stabilizing mechanisms will be discussed, including: 1) oxygen vacancies, which in pure HfO₂ will be shown to exist in concentrations >20% and whose impact on phase stability appears to be greater than crystallite size and 2) mechanical stress, particularly the role of the top electrode, which serves as an out-of-plane rather than in-plane mechanical constraint. It will be shown that often-cited thermal expansion mismatch of the electrodes and hafnia layers is not consistent with the hafnia film stresses measured and is not a valid explanation of the so-called electrode capping effect. Finally, using synchrotron-based diffraction and spectroscopy, we will show how the phases evolve as the ferroelectric is poled and cycled and how this leads to performance instabilities. Finally, it will be shown that the presence of the non-ferroelectric tetragonal phase may be overstated and that an antipolar (e.g. truly antiferroelectric) orthorhombic phase with space group Pbca is common in hafnium zirconium oxide films and can better explain the observed electrical, vibrational, and mechanical behaviors.

Ferroelectric Hf_0.5Zr_0.5 O₂ (HZO) has attracted much attention for non-volatile memory applications since HfO₂ is already used as a gate dielectric. For efficient integration, knowledge about how HZO interacts with electrode materials is necessary. IPE provides a method to observe interfacial energy barrier heights "in-situ" in working devices. We previously reported the barrier heights in as-deposited HZO in metal insulator metal structures (MIM) [2]. However, both post deposition/metallization annealing, "waking", and "poling" are necessary to stabilize and exploit the ferroelectric behavior [1]. To date, there have not been reports of IPE barrier measurement on woken and poled HZO in metal oxide semiconductor (MOS) structures.

In this study, atomic layer deposition was used to deposit 20 nm HZO on a degenerately doped p-Si using 102 supercycles of TDMAH (HfO₂) and TDMAZ (ZrO₂). Next, a blanket 20 nm TaN film was deposited and annealed for 30 seconds at 600°C. This TaN layer was then stripped and replaced by an optically transparent electrode of 5nm TaN and 5 nm Pd. Waking was done using a 5000 cycle 1 kHz square wave with magnitude +/- 5V. Once a device was woken, it was poled using a single voltage pulse of +-4V. IPE measurements were done by focusing a single wavelength of light on the device surface while applying a voltage (V_app) between the Si and grounded top electrode and sweeping photon energy from 1.7 eV to 5.5 eV while measuring IPE current. The measurement is repeated at 0.1V increments from -1.5 to 1.5 V. IPE current thresholds were extracted at each applied voltage, V_app, and plotted vs. V_app^1/2. This plot was extrapolated to zero voltage to obtain the band offsets between the TaN and the Si conduction band (CB) and valence band (VB) and the HZO VB.

For pristine devices the TaN, Si CB, and Si VB barriers were measured at 2.5 eV, 3.5 eV, and 4.4 eV, respectively. Following waking, the TaN barrier was reduced to 2.1 eV, possibly indicating redistribution of oxygen defects toward the TaN interface. The Si CB and VB remained roughly the same at 3.4 and 4.6eV, respectively. The barriers of positive poled devices were within error of the woken devices, but the negative poled devices showed an increase in the TaN barrier to 2.8 eV and a decrease in the Si CB and VB barriers to 3.1 and 4.4 eV respectively. This suggests oxygen vacancy movement away from the TaN interface. IPE measurements give new insight into HZO devices operation. C-V and I-V measurements will be discussed at conference.

[1]E. D. Grimley et al., AEM2 1600173, (2016)

[2]M. A. Jenkins et al., ACS AMI 13, 14634–14643, (2021)

Biaxial stress has been identified to play an important role in the stability of the ferroelectric phase in hafnium oxide-based thin films. However, thus far, the stress state during wake-up has not been quantified. In this work, the stress evolution with electric field cycling in hafnium zirconium oxide capacitors is evaluated. The remanent polarization of a 20 nm thick hafnium zirconium oxide thin film increases from 13.8 μC/cm² in the pristine state to 17.6 μC/cm² following 10⁶ field cycles at 2.5 MV/cm. This increase in remanent polarization with field cycling is accompanied by a decrease in relative permittivity of approximately 1.5, which could indicate that a phase transformation has occurred. The presence of a phase transformation is confirmed by nano-Fourier transform infrared spectroscopy measurements that show an increase in the ferroelectric phase after wake-up. Using an X-ray diffractometer with a collimated source and a two-dimensional detector, diffraction patterns from individual devices electric field-cycled from 0 to 10⁶ cycles are collected and stress quantified using the sin²(ψ) technique. The biaxial stress was measured in several stages of wake-up and was observed to decrease from 4.3 ± 0.2 to 3.2 ± 0.3 GPa. This work provides new insight into the mechanisms associated with polarization wake-up in hafnium zirconium oxide.

Today’s nanoelectronics are reaching limits of energy and speed with conventional materials and traditional layouts that separate logic and memory. For tackling this grand challenge, phase-change memory (PCM) holds promise for both digital memory and brain-inspired computing.^1,2 However, PCM based on traditional phase-change materials like Ge₂Sb₂Te₅ (GST) suffers from high switching power and resistance drift, limiting its potential.¹

Here, using novel chalcogenide superlattices (SL) and leveraging their unique structural and electro-thermal properties, we realize ultralow-power PCM both on rigid and flexible substrates. Using SLs of alternating thin layers of Sb₂Te₃ and GeTe or GST, we achieved ~8-10x lower switching current density in superlattice-PCM on rigid silicon substrates, compared to conventional GST PCM.³ Our SLs are sputter-deposited at low temperatures (200 °C), compatible with CMOS back-end-of-line processing. Electro-thermal confinement in the superlattice material enhances the heating efficiency, enabling a dramatic reduction of switching energy in such PCM, as confirmed by our transport measurements and electro-thermal simulations.⁴

We also uncovered a key correlation between the SL interfaces and PCM device performance. We found that both switching current and resistance drift decrease as the SL period thickness is reduced, however, SL interface intermixing increases both.⁵ As the SL period thickness is reduced, a greater number of van der Waals (vdW) interfaces limits cross-plane thermal transport, but if the SL interfaces are intermixed, the thermal conductivity can increase, due to the loss of vdW gaps.

We also integrated these superlattices directly onto flexible polyimide substrates in a confined memory cell, achieving further energy efficiency. Our flexible SL-PCM devices show record-low switching current density⁶ of 0.1 MA/cm², ~100x lower than commercial PCM. This memory also shows multi-level operation, promising for Internet-of-Things devices on flexible substrates.

In summary, we achieved ultralow-power switching in nanoscale phase-change memory based on chalcogenide superlattices. Our results demonstrate how combining versatile material functionalities and their transport fundamentals can unlock decade-spanning advances in energy-efficient memory for heterogeneously integrated nanoelectronics.

Refs: 1. S. Raoux et al., MRS Bull.39, 703 (2014); 2. A. Sebastian et al., Nat. Nanotech.15, 529 (2020); 3. A.I. Khan, E. Pop et al., IEEE EDL 43, 204 (2022); 4. H. Kwon, E. Pop et al., Nano Lett. 21, 5984 (2021); 5. A.I. Khan, E. Pop et al., Nano Lett. 22, 6285 (2022); 6. A.I. Khan, E. Pop et al., Science 373, 1243 (2021).