AVS 71 Session CPS+MS-ThP: CHIPS Act: Semiconductor Manufacturing Science and Technologies Poster Session

Among the different analytical techniques capable of providing atomically resolved 3D structures with high chemical sensitivity, laser-pulsed Atom Probe Tomography (APT) has emerged as a promising candidate to investigate complex semiconductor devices composed of multiple layers of varying composition. The effects of using a short wavelength laser in APT have been under investigation in recent years, showing an increased survivability of Si/SiO₂/Si test structures using deep-ultraviolet (DUV; λ≈266 nm) over near-ultraviolet (NUV; λ≈355 nm) irradiation [1]. The improved sample yield using a DUV source is attributed to a more continuous and gently varying voltage curve as the sample progresses through the SiO₂ dielectric, thought to indicate a decrease in the relative evaporation fields between Si and SiO­­_2­ compared to NUV experiments. To test whether an even shorter wavelength would result in further benefits, a similar test structure was investigated on the extreme-ultraviolet (EUV; λ≈30 nm) APT system developed at NIST [2]. Comparative EUV and NUV APT experiments revealed that the apparent relative evaporation fields between Si and SiO₂ are inverted in EUV experiments, evidenced from the magnitude of the voltage curves collected under a constant detection rate. The lower apparent evaporation field of SiO­₂ relative to Si under EUV illumination suggests that the evaporation field may not be fully described as a material-based constant. In addition to the changes in the EUV voltage curve through the dielectric layer in this test structure, changes to the apparent background and other experimental variables important for semiconductor devices investigated using APT suggests that a single wavelength may not be ideal for every layer of a material with varying composition.

References:

1. Prosa, T., Lenz, D., Martin, I., Reinhard, D., Larson, D., & Bunton, J. Microscopy and Microanalysis, 1262–1264 (2021) 27-S1.
2. Caplins, B. W., Chiaramonti, A. N., Garcia, J. M., Sanford, N. A., & Miaja-Avila, L. Review of Scientific Instruments, 093704 1-13 (2023) 94.

As the continuous scaling of Dynamic Random Access Memory (DRAM) technology, semiconductor industry is evolving from two-dimensional (2D) to three-dimensional (3D) DRAM to provide the massive amounts of memory required for AI applications. 3D DRAM is expected to require advanced processes (deposition, etching and doping capabilities) to shape and form increasingly precise 3D structures across a 300mm wafer. In this work, a methodology for characterizing the nano structure of 3D DRAM to optimize these various processes is introduced as a promising solution to overcome current metrology limitation in semiconductor industry. Virtually reconstruction of 3D DRAM by hundreds of 2D Scanning Electron Microscopy (SEM) images is successfully demonstrated, offering superior detailed 3D nanostructure and extending the traditional SEM or Transmission Electron Microscopy (TEM) capability. Quantitative analysis on the reconstructed 50-pair Si/SiGe multilayers 3D DRAM is presented with excellent results in the measurements of 2D/3D Critical Dimension (CD) and defectivity.

Since global trade disruption highlighted supply chain vulnerabilities, domestic semiconductor manufacturing has emerged as a national priority, as evidenced through passage of the CHIPS and Science Act in 2022. With this boost in spending comes the risk of workforce shortages, with as many as 58% of new jobs at risk of being unfilled [1]. In Vermont, IBM Microelectronics (now GlobalFoundries) have had a continuous presence since 1957, creating a robust ecosystem of semiconductor manufacturing and design expertise, however local workforce challenges remain. While Vermont has a 91.2% high school completion rate, only 57% of those age 18-24 go on to attend an institution of higher education [2]. Traditionally, microelectronics and semiconductor concepts are not covered in the K-12 curriculum, leaving nearly half the population underinformed about a vital employment industry.

In this work we bridge the microelectronics education gap in Vermont through a workshop developed to educate K-12 science teachers, enabling them to more confidently introduce concepts in the classroom and informal settings. The developed workshop was run for the first time in June of 2025 and covered topics such as electrical prototyping, board and integrated circuit design, programming microcontrollers, interfacing with sensors, microelectronics fabrication, and advanced robotics. Activities were developed such that they could be run in a K-12 setting using the kits provided to teachers during the workshop. Materials have been published at the program website for free use [3]. The initial cohort consisted of 13 teachers from across the state whose instructional focus varied from 4^th through 12^th grade. Feedback from the attendees will be presented, along with learnings and considerations for any others hoping to offer a workshop like this in their jurisdiction.

[1] “Chipping Away” Report, Semiconductor Industry Association. July 2023.

[2] American Community Survey Table S1501, 2023 5-yr estimates. https://data.census.gov/table/ACSST5Y2023.S1501?g=040XX00US50. Accessed 08/2025.

[3] UVM SPARK. https://sites.google.com/view/spark-vtk12/home. Accessed 08/2025

This work was supported by NSF grant No. 2119485 and the V-GaN Tech Hub.