AVS 72 Session EM-TuA: Pioneering Directions in Logic and Memory Devices and Materials: AI Hardware, Microelectronics, 2D Materials, Processing, Interconnect, Heterogeneous Integration, Energy Cooling

When atoms are confined to atomically thin two-dimensional (2D) lattices, they host many electronic behaviors that simply do not exist in bulk crystals, putting 2D materials at the heart of next-generation electronic and quantum technologies. Beyond their reduced dimensionality, 2D materials possess another remarkable feature: like a sheet of paper, they can bend, wrinkle, and undulate. These topographical deformations are not merely structural imperfections; they can act as powerful design knobs that generate new electronic phenomena absent in pristine flat systems. In this talk, I will present how quantum ab initio theoretical calculations can be used to explore topography as a design principle for discovering exotic electronic behavior in 2D materials. I will discuss how engineered undulations in monolayers generate pseudo-electric and pseudo-magnetic fields, enabling electron-optics effects [1], one-dimensional correlated electronic states [2], artificial quantum wells [3], and long-lived persistent spin-helix textures [4] relevant to spintronics. These examples show that controlled curvature and strain can transform simple 2D crystals into platforms for emergent quantum functionality. More broadly, this work points toward a new design paradigm, curvatronics, where geometry and topography are used as active ingredients for engineering quantum materials.

[1] Nano Lett. 22, 2934–2940 (2022)

[2] Nature Communications 13, 3103 (2022)

[3] Physical Review B 112, 115308 (2025)

[4] Matter 8,102378 (2025)

Atomically thin semiconductors are a leading platform for next-generation electronic, photonic, and quantum devices. Their promise depends on synthesis methods that deliver crystalline quality and uniformity rivaling exfoliated flakes, a standard that grown monolayers have historically failed to meet. In this talk, I will present advances in chemical vapor deposition (CVD) of transition metal dichalcogenides (TMDs) driven by deliberate control of the reactor environment: tuning precursor oxidation state, promoting salt-flux transport, and managing trace impurities to improve nucleation, reduce defect densities, and bring polytype and doping under direct control.

For solid-source CVD growth of WSe₂, uncontrolled oxyselenide formation and residual impurities can seed parasitic nucleation and degrade film quality. We address this with a targeted pre-annealing strategy that removes contaminant phases and yields a chemically more uniform, kinetically favorable precursor [1]. The resulting monolayer WSe₂ shows improved uniformity, grain sizes of ~10-30 µm, and charged defect densities below 10¹⁰ cm^-2 as quantified by conductive AFM, enabling high-performance monolayer p-type transistors with on-state currents up to 888 µA/µm.

To extend these controls to wafer-scale synthesis and systematic chemical tuning of WS₂ and WSe₂, we employ metal-organic chemical vapor deposition (MOCVD) and a hybrid approach that uses solution-processed transition-metal salt precursors [2]. This route enables repeatable control of substitutional doping, alloy composition, and polytype, including selective formation of the ferroelectric 3R phase under confined-space growth conditions [3]. Across both platforms, machine-learning-enhanced hyperspectral reflectance microscopy provides rapid, spatially resolved feedback at high throughput [4]. We further implement locally engineered dopant gradients during MOCVD to program lateral carrier density profiles.

The rapid expansion of AI and IoT demands computing systems capable of efficiently processing trillion–scale datasets. Conventional Von Neumann architectures, which separate memory and computation, suffer from severe energy inefficiencies due to frequent data transfer and raise sustainability concerns because of their reliance on inorganic, non–renewable materials. Neuromorphic computing offers a compelling alternative by mimicking the brain’s ability to store and process information within the same physical structure. Resistive switching memory (RSM) is a key enabling technology, as they integrate memory and computation in a single device. When implemented using renewable and biodegradable natural organic materials, RSM can further advance environmentally sustainable neuromorphic systems.

Conventional 1T1C DRAM faces fundamental scaling limitations due to the use of capacitor, leading to challenges in maintaining sufficient charges as device dimension shrinks. To address this issue, capacitor-less memory architectures such as 2T0C DRAM have been proposed, offering improved scalability (4F²) and longer retention characteristics. Amorphous oxide semiconductor thin film transistors (TFTs) are actively investigated for 2T0C DRAM due to their excellent uniformity, high mobility, low off-current, and back-end-of-line (BEOL) compatibility.

2T0C DRAM consists of two transistors, which are write transistor (W_TR) and read transistor (R_TR). Drain of the W_TR is connected to gate of the R_TR, and the connected line serves as the storage node (SN). During the write operation, gate voltage higher than the threshold voltage is applied to the W_TR, and the charge is stored in the SN by applied bias at the source of W_TR. Then, the electric field induced by the stored charges in the SN turns on the channel of the R_TR. Therefore, by reading the drain current of R_TR, whether charge is stored (memory state 1) or not (memory state 2) in the SN can be detected. Because the amount of stored charges in the SN controls the R_TR conductance, the multi-level operation (> 2 memory states) is thought to be feasible, dependent on the channel properties of R_TR. For this reason, employing the R_TR with higher subthreshold swing would increase the distinguishable state ranges, thereby enabling a greater number of multi-level states. Not just for the stand-alone memory applications, the multi-level memory states of 2T0C DRAM could be employed for processing-in-memory (PIM) operations by updating and inferring the conductance as synaptic weight.

In this work, multi-level operation characteristics of the IGZO homogeneous 2T0C, e.g., IGZO channel for both W_TR and R_TR, and heterogeneous 2T0C with IGZO channel for W_TR and ZnO channel for R_TR, were compared. IGZO channel exhibits a low off-current and low subthreshold swing (279 mV/dec), which enables a long retention time and clear binary memory application when used as W_TR and R_TR, respectively. For the R_TR of heterogeneous 2T0C, ZnO channel layer showed higher subthreshold swing (1455 mV/dec) than the IGZO. Adopting these multi-level conductance characteristics of R_TR, the pattern recognition accuracy for MNIST patterns was evaluated as benchmark for PIM applications.

3D flash memory scaling continues to increase the structural and electrical demands on word line metallization, where film conformality, resistivity, void control, stress, and integration compatibility directly affect array performance and yield. Conventional tungsten-based word line schemes have provided manufacturable solutions for multiple generations; however, continued pitch scaling, higher aspect ratio structures, and longer replacement depth increasingly expose the limitations of traditional CVD tungsten processes, including nucleation-layer non-conformality, fluorine-related concerns, and resistance scaling. As a result, alternative deposition methods and metal systems are being actively evaluated to support future generations of 3D flash memory.

This presentation reviews the evolution of 3D flash memory word line metallization from CVD-dominated tungsten integration toward more advanced ALD-enabled metal fill approaches, with particular emphasis on the transition from tungsten to molybdenum. We compare key process and material considerations, including precursor chemistry, nucleation behavior, step coverage, impurity control, film continuity, and compatibility with high-aspect-ratio structures. The discussion highlights how ALD-based approaches can provide improved thickness control and conformality, while also introducing new challenges in productivity, stress management, and interface engineering.

In addition, we examine the motivation for molybdenum as an alternative word line metal, focusing on its potential benefits in resistance scaling, integration flexibility, and compatibility with future array architectures. Process tradeoffs between tungsten and molybdenum are discussed from both device and manufacturing perspectives, including metal resistivity, liner requirements, thermal stability, etch/clean compatibility. Case studies are used to illustrate how deposition methods and material selection jointly influence word line resistance, structural fill quality, and downstream integration margin.

Overall, this presentation summarizes the opportunities and challenges associated with next-generation word line metallization for 3D flash memory. By connecting process evolution from CVD to ALD with material evolution from tungsten to molybdenum, this work provides an integration-focused framework for evaluating future metallization schemes. These findings suggest that successful word line scaling will require co-optimization of metal selection, deposition chemistry, nucleation control, and array integration design to balance electrical performance, manufacturability, and long-term technology extendibility.

Computational technologies based on functional oxides have the potential to dramatically reduce energy consumption due to properties such as loss-free switching and nonvolatility. One of the primary challenges with these technologies, however, is that epitaxial deposition is often incompatible with silicon. Here, we demonstrate scalable, epitaxial deposition of ferroelectric oxides on silicon. We utilize magnetron sputtering to deposit high quality perovskite oxides on SrTiO3 buffered substrates. Electrical measurements show ferroelectric switching down to 100s of mV, firmly within the realm of potential CMOS integration, as well as the nonvolatility that is expected from high-quality ferroelectric materials. Additionally, the use of Si substrates allows for significantly more advanced device integration than what would be possible with the single crystalline oxide substates that are normally used for epitaxy.

Ferroelectric hafnium oxide (HfO₂)-based FeFETs have attracted considerable attention for fast, low-power, and high-density non-volatile memory applications, with advantages of stable spontaneous polarization, non-volatility, and full CMOS compatibility. A single-transistor architecture modulates a threshold voltage (V_th) between two distinct polarization states via a ferroelectric gate, suitable for both high-density storage and neuromorphic computing. Nevertheless, conventional FeFETs are fundamentally constrained by the fixed remnant polarization (P_r), which limits the memory window (MW) and consequently narrows the read margins between discrete V_th states, posing a critical challenge for reliable Multi-Level Cell (MLC) operations.

In this study, we investigate electrically tunable remnant polarization via oxygen ion exchange in Al-doped HfO₂ (HAO) ferroelectric layer with ion reservoir layer, where polarization is enhanced by the increase of oxygen vacancy concentration in the HfO₂ lattice. To implement oxygen vacancy exchange with HAO, we propose a Metal-Insulator-Ferroelectric-Metal (MIFM) structure incorporating a low-temperature deposited HfO_2-x as a high defect-density reservoir layer of oxygen ions. The device exhibits a distinct and controllable 2P_r window of approximately 7 µC/cm², modulating between 21 and 28 µC/cm², enabling a tunable and broadened MW with V_th shift for stable multi-level operations. Specifically, the polarization state of the HAO layer remains stably upon low-voltage pulse application, whereas oxygen vacancy migration between the HAO and HfO_2-x reservoir layer occurs, tuning the polarization state under high-voltage or repetitive pulse application. This tunable remnant polarization is attributed to the changes in oxygen vacancy concentration in the ferroelectric layer, thereby modulating the fraction of the ferroelectric orthorhombic phase.

This tunable remnant polarization can be applied to the FeFETs by constructing MIFS(Metal-Insulator-Ferroelectric-Si) capacitor stack, where applying the gate bias induces the remnant polarization of HAO and consequently modulates V_th shift for memory operation. Moreover, the P_r values can be further increased by high voltage application, which enhances MW and enables more reliable MLC operation.

In conclusion, we propose a novel method for enhancing MW and V_th controllability via electrochemical ionic modulation in HAO-based ferroelectric devices. By incorporating a low-temperature HfO_2-x reservoir layer, oxygen vacancy migration is effectively facilitated, potentially providing a reliable and reversible pathway for MW expansion and precise multi-level ferroelectric tuning.

Emerging non-volatile memory (NVM) devices have been attracting significant attention due to the increasing demand for data-driven applications.Among various NVMs, charge-trap flash memory (CTF), which operates by modulating the threshold voltage (V_T) via charge trapping, offers the highest storage density with the lowest bit cost. The bit density of CTF has been further increased by employing a three-dimensional structure, i.e., 3D NAND flash. However, as the dimensions of devices keep scaling down, several reliability challenges arise, including reduced memory window, electrostatic interference, and unintended V_T shifts. In particular, the lateral charge migration through the charge-trap layer (CTL) to adjacent cells becomessevere as the distance between cells decreases.

In this study, the improved NVM characteristics of CTF device are demonstrated by employingmulti-layered nanocrystal (NC) CTL deposited by atomic layer deposition (ALD), herein referred to as NC-CTL. The NC-CTL composed of physically and electrically isolated NCs enables potentially to store charges more reliably even in the highly scaled-down architecture bysuppressinglateral charge migration, unlike a continuous layer-type CTL. In addition to geometric modulation, NC material engineering could control NVM characteristics by modifying the energy-band structure of the devices. Notably, the discrete HfO₂ and ZnO NCs were uniformly deposited with high density by controlling the number of ALD cycles. In the device with ALD-HfO₂ NCs, the wider bandgap of HfO₂ reduces the kinetic energy of injected electrons during programming, leading to more uniform charge trapping throughout the NC-CTL and enabling a wide memory window. For comparison, the device with ZnO NC-CTL having a narrower bandgap exhibits a smaller memory window, attributed to the existence of a dead zone in the NC-CTL near the tunneling oxide, where high-energy electrons injected into the NC-CTL are less likely to be trapped. It highlights the impact of energy-band structure of CTL to achieve a wide memory window. Moreover, memory performance such as programming efficiency and reliability properties could be enhanced by adopting SiO₂/Al₂O₃ bi-layered blocking oxide and rapid thermal annealing processing, achieving a memory window of >7 V at programming voltage of +20 V and retention of ~91 % after 12 hours. These results demonstrate that the use of multi-layered NC-CTL is a promising strategy to simultaneously enlarge a memory window and achieve stable retention, thereby enhancing the reliability of highly scaled 3D NAND flash.

Acknowledgement

This work was supported by Samsung Electronics Co., Ltd(IO260312-15875-01)

Cooling of people and places consumes massive amounts of energy and is anticipated to rise 45 % by year 2050 (IEA 2023). Passive daytime radiative cooling (PDRC) is an emerging net-zero energy cooling method where warm surfaces emit radiation to the cold of deep space (4 K) through the atmospheric transmission window (wavelengths of 8-13 micron). By virtue of their chemical structure, polymeric materials naturally emit in this region. However, to reach a net-cooling effect, materials must simultaneously prevent heat gain from the absorption of solar radiation. In polymers, this is commonly achieved via scattering from pores where pore length scales are designed to correspond to the wavelengths of the solar spectrum. While multiple methods have emerged to created porous polymers for PDRC, most lack interconnected pores which impacts mechanical properties and reduces moisture vapor transport. Mirroring the network structure observed in the Cyphochilus beetle, we have developed a scalable method to create porous polymer films with broadband solar rejection (R_solar > 96 %), high levels of moisture vapor transport, and durable optical properties. In this talk, we will explore how polymer processing influences characteristic length scales in these materials and their resultant optical performance. Through process optimization, this scalable structure is found to be particularly attractive for rugged use PDRC applications where movement and moisture transport are key.