IWGO 2026 Session IWGO-WeA: Advanced Device Scaling and Fabrication Techniques I

The ultrawide-bandgap semiconductor β-gallium oxide (Ga₂O₃) has emerged as a promising material for power electronics, RF, and high–speed switching applications. This talk presents recent advances in Ga₂O₃ device technologies developed by our group. We demonstrate lateral Ga₂O₃ MOSFETs incorporating optimized field–plate designs that achieve beyond–kilovolt breakdown voltages, along with their switching characteristics under electrical stress conditions. The role of in situ Mg–doped MOCVD-grown Ga₂O₃ films as efficient current–blocking layers (CBLs) is discussed. In addition, trench MOSFET architectures incorporating CBLs are presented for high–voltage, high–speed operation targeting grid–level power applications. Strategies for mitigating thermal management challenges in Ga₂O₃ devices are also addressed.

Owing to its high Johnson’s figure of merit, Ga₂O₃ is also a strong candidate for high power density RF amplifiers. We report significant improvements in RF power performance using Ga₂O₃ technology. By aggressively scaling gate lengths and gate–source spacing, (AlₓGa₁₋ₓ)₂O₃/Ga₂O₃ heterostructure FETs were fabricated, demonstrating record RF performance. We will also report the radiation tolerance of the RF devices.

β-Ga₂O₃ heterojunction diodes (HJD) incorporating different p-type oxides (NiO_x, Cu₂O, Cr₂O₃) have been demonstrated with multi-kV-class breakdown voltages. In this work, we report the first experimental demonstration of kV-class static and switching performance of Cr₂O₃/β-Ga₂O₃ heterojunction diodes (HJD) with > 3 kV breakdown voltages. The devices were fabricated on (001)-oriented 9.5 µm thick β-Ga_₂O_₃ drift layer grown by halide vapor phase epitaxy (HVPE) on a conductive β-Ga_₂O_₃ substrate. Bi-layer Cr₂O₃ and anode metal (Ni/Au/Ni) were lifted off simultaneously to fabricate the HJD. A 1.5 μm mesa etch was employed to realize an effective edge termination. The fabricated HJDs exhibited a forward current density of 125 A/cm² at 4.5 V and a differential specific on-resistance of ~19 mΩ·cm². Breakdown voltage of ~3.2 kV was achieved for a wide range of device dimensions (diameter = 60-300 μm) with noise floor reverse leakage up to 2.5-3 kV. This is a significant achievement since breakdown voltage showed no substantial degradation with increasing device dimensions [1]. Based on a punch-through model, the estimated parallel-plane breakdown field approached ~ 4 MV/cm. In addition, the switching performance of β-Ga₂O₃ power diodes is critical for high-frequency power conversion applications. A double pulse test (DPT) was employed, where Ga_₂O_₃ HJD served as the upper device and a commercially available SiC MOSFET served as the lower switching device. At a reverse voltage of 1.5 kV and a peak forward current of about 0.6 A, the HJD showed a peak reverse recovery current (I_rr) of −0.128 A, a reverse recovery time (t_rr) of 12.8 ns, and an ultralow reverse recovery charge (Q_rr) of 0.74 nC. This is the highest test voltage and lowest reverse recovery charge reported for the β-Ga₂O₃ diode switching test. Additional measurements at 1 kV with peak forward currents ranging from 0.3 to 0.7 A showed relatively stable I_rr, t_rr, Q_rr at 0.1 A, 15 ns, and 0.6 nC, respectively. In comparison with a commercial SiC MPS diode exhibiting Q_rr of 41 nC and t_rr of 20 ns at 1.2 kV, the Cr_₂O_₃/β-Ga_₂O_₃ HJDs reported here show improved reverse recovery characteristics. In summary, we have achieved > 3 kV breakdown voltages with 4 MV/cm parallel plane electric field for a wide range of device dimensions by fabricating Cr₂O₃/β-Ga₂O₃ heterojunction diodes (HJD) with an optimized edge termination. The combination of multi-kV static breakdown voltages with sub-nC reverse recovery charge at 1.5 kV test voltage highlights the strong potential of Cr_₂O_₃/β-Ga_₂O_₃ HJDs for future medium-voltage and high-frequency power conversion applications.

[1]. Liu, AIP Advances, 15, 015114 (2025).

The β-Ga₂O₃ has achieved great interest for high-power devices due to its large critical breakdown field, shallow dopants, and melt-grown native substrates. To achieve the desired multi-kV β-Ga₂O₃ power switches, vertical devices with low-doped, thick drift layer and minimal defects are essential requirements. However, to date, scaling up the voltage rating of vertical β-Ga₂O₃ devices has remained severely limited due to the presence of killer dislocation defects and unintentional [Cl] impurities that creates difficulties in achieving high-quality thick drift layer (>10 μm) and lower doping (<8×10¹⁵ cm^-3) with the existing (001) β-Ga₂O₃ epiwafers grown by halide vapor phase epitaxy (HVPE). To overcome these constraints, the recently emerged HVPE (011) β-Ga₂O₃ epiwafers has brought tremendous potential by offering reduced dislocation effects due to the dislocation being parallel to the (011) plane as well as low unintentional [Cl] impurities [1]. However, due to their early stage, high-power vertical Schottky barrier diodes (SBD) on (011) β-Ga₂O₃ epiwafers are yet to be reported.

In this work, we report high-voltage vertical (011) β-Ga₂O₃ SBDs on HVPE-grown 20 μm thick drift layer with 1 MHz C-V extracted doping ~5×10¹⁵cm^-3. Two different Schottky contact diodes were co-fabricated with 100 μm diameters, including Pt/β-Ga₂O₃ and PtO_x/thin Pt (1.5 nm)/β-Ga₂O₃. The PtO_x/thin Pt contact merges the benefits of both low turn-on voltage from interfacing Pt while allowing improved reverse blocking by PtO_x [1]. To reduce edge field crowding, we integrated high-permittivity (κ) ZrO₂ field-plate (FP) for both contacts using a stack of sputtered ZrO₂ (226 nm) on interfacing thin ZrO₂ (9 nm) formed by atomic layer deposition to protect the surface from sputter damage. The forward J-V showed excellent transport properties with near unity ideality factor and similar turn-on voltage for both cases. At reverse bias, the SBDs without FP revealed similar breakdown voltage of ~1.5 kV for both cases. However, with FP, the PtO_x/thin Pt SBDs showed significantly enhanced breakdown voltage ~3.7 kV compared to the Pt ones (2.75 kV) and punch-through field with a peak of 5 MV/cm at FP edge, reaching ZrO₂ breakdown limit. Moreover, the FP PtO_x/thin Pt SBDs demonstrated ultra-low leakage which is order of magnitude lower compared to existing reports of (001) β-Ga₂O₃ SBDs of same 100 um diameter at 3 kV operation. To the best of our knowledge, this is the first report of high-power vertical (011) β-Ga₂O₃ SBDs that shows its great potential to expand the performance limit of low-loss multi-kV β-Ga₂O₃devices.

[1] E. J. Hollar and E. Farzana, Appl. Phys. Lett. 128, 053503 (2026).

Normally-off operation is highly demanded for FETs to ensure fail-safe capability in high-voltage and high-power applications. Enhancement-mode (E-mode) Ga₂O₃ current aperture vertical FETs (CAVETs) fabricated using room-temperature Si- and nitrogen (N)-ion implantations have been demonstrated [1]. Overall on-state device characteristics of the CAVETs were decent; however, the off-state breakdown voltage (V_br) was as low as 263 V [1], which could be attributed to the insufficient recovery of crystal damage caused by the implantations. In this work, we employed hot ion implantation to minimize the crystal damage and enhance V_br.

We used n-Ga₂O₃ (001) epitaxial substrates having an n^--Ga₂O₃ drift layer grown by halide vapor phase epitaxy. The CAVET fabrication process started with N hot implantation. N ions with a dose of 1 × 10¹⁴ cm^-2 were implanted into the n^--Ga₂O₃ drift layer at 450ºC, followed by activation annealing at 1000ºC for 20 min in N₂ atmosphere. Subsequently, multiple Si implantations were performed at 300ºC to form an n-channel layer, n⁺-access regions, and n⁺⁺-drain and source ohmic regions. The activation annealing of the Si implants was carried out at 800ºC for 30 min. A 50-nm-thick Al₂O₃ gate dielectric was formed by atomic layer deposition on the channel layer. Source and drain ohmic electrodes, and gate electrodes were fabricated with Ti/Au and Ti/Pt/Au metal stacks, respectively. The aperture size and the Si-implanted channel area were 20 μm and 210 × 25 μm², respectively.

Drain current–drain voltage (I_d–V_d) characteristics showed that at a gate voltage (V_g) of + 6 V, the CAVET exhibited near-linear I_d turn-on behavior in the low V_d range and quasi-saturation at V_d ~ 20 V, and reached the maximum I_d of 0.123 kA/cm² at V_d = 40 V. The I_d–V_g characteristics at V_d = 20 V provided a high I_d on/off ratio of 1 × 10¹¹, which can be attributed to superior current-blocking capability of the N-implanted region formed by hot implantation. The threshold V_g extracted from linear extrapolation of the I_d–V_g curve was + 3.8 V, ensuring the E-mode normally-off operation. The off-state I_d leakage at V_g = 0 V monotonically increased with increasing V_d and saturated at 10^-3 – 10^-2 A/cm² for V_d > 100 V. Then, destructive breakdown occurred near the gate electrode edge at V_d = 756 V. All on- and off-state device characteristics of the CAVET in this work were superior to those of the previous one [1]. Among the improvements, the most significant was the threefold increase in V_br. These results indicate that the hot implantation process is effective in improving endurance of Ga₂O₃ CAVETs.

[1] M. H. Wong et al., IEEE Electron Device Lett. 41, 296 (2020).

Due to its large bandgap (~4.8 eV) and strong critical electric field (~8 MV/cm), β-Ga₂O₃ has drawn a lot of attention as an ultra-wide-bandgap (UWBG) semiconductor for high-power applications. However, because traditional n⁺ contact methods rely on ion implantation followed by high-temperature activation annealing, which increases process complexity and may degrade material quality, the realization of cost effective and low-resistance ohmic connections is still difficult. In this work, we reduce thermal budget while preserving electrical performance by using a regrown n⁺ contact layer to create highly doped contact areas without post-implantation annealing.

The fabrication process started on commercially available Sn-doped (001) β-Ga₂O₃ substrates with a ~10 µm HVPE-grown epitaxial drift layer. The CBL was formed by N-ion implantation at multiple energy levels followed by annealing in N₂ atmosphere to activate the nitrogen dopants. In contrast to the conventional approach of using Si-ion implantation for ohmic contact formation, which requires additional high-dose implantation steps, dedicated masking, and high-temperature activation annealing, this work introduces a regrown Si-doped n⁺ contact layer (~75 nm) with a high carrier concentration of ~10¹⁸ cm⁻³ deposited directly by MOCVD epitaxial regrowth.

The ohmic contact quality was validated by transmission line model (TLM) measurements, yielding a transfer length L_T = 0.13 µm, contact resistance R_C = 0.38 Ω·mm, sheet resistance R_SH = 1389 Ω/sq, and specific contact resistivity ρ_C = 2.65 × 10⁻⁷ Ω·cm². Transfer characteristics demonstrated normally-off operation with a clear threshold voltage of V_TH = 5V and an I_ON/I_OFF ratio of 8.5 × 10⁵. From the output (I_D–V_DS) characteristics swept with V_GS = 0 to 20 V in 5 V steps, a peak current density exceeding 100 A/cm² was achieved, with an on-resistance R_ON = 94.6 mΩ·cm².

Three-terminal off-state breakdown measurements were performed in Fluorinert (FC-40) liquid to suppress air arcing. At V_GS = 0 V, breakdown voltages of 920 V-980 V were recorded across three representative devices, demonstrating excellent device-to-device uniformity and robust blocking capability. The resulting Baliga figure of merit (BFOM = V_BR²/R_ON) makes this work well competitive with state-of-the-art vertical β-Ga₂O₃ devices.

This work demonstrates a high-performance enhancement-mode vertical β-Ga₂O₃ trench-gate MOSFET with N-ion implanted CBL and a simplified ohmic contact scheme based on epitaxial n⁺ regrowth. The regrown n⁺ contact approach offers a practical, cost-effective, and thermally efficient alternative to ion-implanted contacts, without sacrificing electrical performance.